VXI总线四通道LVDS数据传输模块设计

Design of VXI-bus Four-Channel LVDS Data Transfer Module

针对国内测试系统开发中出现的低电压差分信号(LVDS)技术需求提出了一种VXI总线四通道LVDS数据传输模块的设计实现方法;以FPGA作为控制核心,利用Verilog HDL设计实现了VXI接口和HDLC通讯协议设计,并通过基于VXI总线的块传输方式和乒乓存储技术,完成了大批量数据的接收;另外,为确保LVDS信号的完整性,结合实际设计和调试经验,文中还分析了LVDS接口信号印制板布线和布局问题;该模块已用于测试系统开发,并实现了测试系统与被测设备的视频信号传输;应用结果表明,模块传输速度为4Mbit/s时误码率小于10-6。

To fulfill the needs in the test system development for Low Voltage Differential Signal （LVDS）, a design is provided to achieve a VXI bus four--channel LVDS data transfer module. The FPGA is adopted to make control unit, and the VXI--bus interface and data transfer protocol are developed with Verilog HDL. Furthermore, to complete high--throughput data receive, block transfrer in VXI bus and ping--pang memory structure are used. Then, to get a better signal integraty of LVDS signal, tricks for routing and partioning in PCB design is analyzed according to the practical design and debug. This module has been applied in a test system. It solved the video signal transfering between the test system and the UUT. Practical application and test results show that the avarage transfering speed is 4Mbit/s with a bit error rate less than 10^-6.