容易产生测试的电路

ETG ( Easy Test Generation ) Circuits

集成电路技术的快速发展带来了集成电路芯片测试的困难。可测试性设计(DFT)技术被提了出来。这些技术的主要缺点是影响电路性能,而且要求长的连续测试方法。本文给出容易产生测试(ETG)电路的概念。ETG电路是这样一种电路,产生它的完全测试集的计算复杂性与电路大小成线性关系。本文首先解释了ETG与其他DFT方法的区别,然后简单地描述了ETG组合电路、ETG时序电路,特别详细地介绍了ETG PLA。给出了把给定PLA修改为ETG PLA的算法,以及一些新的实验结果。ETG PLA作为ETG电路的一个例子说明了ETG技术的可行性。

Rapid advances in IC technology are causing difficulties with testing of IC chips.Design For Testability(DFT)techniques have been proposed. Major disad vantages of these techniques are the degradation of circuit performance and the req uirement of a long and contiauous test mode. This paper presents a concept of an ETG ( Easy Test Generation ) circuit. An ETG circuit is one for which a complete test set ( covering all modeled faults ) can be generated with linear computational complexity in the circuit size.This paper first explains the difference between ETG and other DFT techniques,and then briefly describes ETG combinational circuits and ETG sequential circuits, and especially discusses ETG PLAs ( Programmable Logic Arrays ) in detail.An algorithm to modify a given PLA into an ETG PLA is prese nted, and some experimental results are given.As an example of ETG circuits,ETG PLAs show the feasibility of the ETG techniques.