临界路径跟踪——测试产生与故障模拟的一种算法

Critical Path Tracing-An Algorithm for Test Generation and Fault Simulation

现有的数字电路测试产生算法,如D-算法、PODEM算法和FAN算法等,几乎都是针对每个给定的故障先求出它的一个测试,然后用故障模拟方法求出该测试所能检测的全部故障。测试产生和故障模拟是分两步进行的。本文提出用临界路径跟踪法进行测试产生和故障模拟,它是从电路的初级输出开始向电路的初级输入进行所谓临界路径跟踪。测试产生和确定该测试所能检测的故障是同时进行的,把测试产生和故障模拟紧密地结合在一起。 和PODEM算法、FAN算法一样,我们限于讨论组合电路中引线s-a-0和s-a-1的单故障。文中详细叙述了临界路径跟踪的策略,保证求得的测试集能覆盖电路中全部可测故障。测试的总数最多不超过电路中每个门单独的测试数的总和。

Presently,almost all the algorithmic test generation methods for digital circuits, such as the D-algorithm,the PODEM-algorithm and the F AN-algorithm,etc., are designed in such a situation where a test is generated first for a given fault and then all faults that can be detected by this test are found out by fault simulation. In this way, test generation and fault simulation are separated iato two different st eps. This paper presents the critical path tracing racthod, a new algorithm for both test generation and fault simulation. The so called 'critical path tracing' is perfor med from primary outputs to primary iaputs in the circuit. The generation of a test and the determination of the faults that can be detected by this test are accomplis hed simultaneously, i.e,,test generation is combined with fault simulation closely. Like the PODEM-algorithm and the FAN-algorithm, the discussion in this paper is limited to the single s-a-0 and s-a-1 faults in combinational circuits.The strategy of critical path tracing is described in detail and it is ensured that all testable faults in the circuit can be detected by the tests generated in this manner. The total number of tests will not exceed the sum of the number of tests for every single ga te.