基于DDR2控制器的主从结构DLL的研究与设计

A Master-slave Delay-locked Loop Structure for DDR2 Controller

提出了一种适用于DDR2控制器的主从结构的DLL的研究与设计,在不同的工艺、电压和温度(PVT)条件下,DLL所产生的时钟保证DDR2在读数据时,数据经过传输线传输后能被正确的采样;写数据时,DLL产生的时钟能精准地控制倍率转化。模拟仿真结果表明在0.13μm CMOS工艺下,该结构具有良好的性能特性,满足设计要求。该结构同样可用于其它需要固定延迟的电路。

Master-slave delay locked loop structure for DDR2 SDRAM＇s controller is presented. The data from DDR SDRAM can be correctly sampled after the transmission in PCB in different process, voltage and temperature （ PVT ）. The accurate clocks supplied by MDLL sample the data from single data rate to double data rate when writing data to SDRAM. The structure is successfully verified by using 0.13 μ m CMOS technology in Virtuoso Spectre simulation. This structure can also be used in other circuits where fixed delays are needed.