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Architecture-Aware Session Lookup Design for Inline Deep Inspection on Network Processors

Architecture-Aware Session Lookup Design for Inline Deep Inspection on Network Processors
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摘要 Today's firewalls and security gateways are required to not only block unauthorized accesses by authenticating packet headers, but also inspect flow payloads against malicious intrusions. Deep inspection emerges as a seamless integration of packet classification for access control and pattern matching for intrusion prevention. The two function blocks are linked together via well-designed session lookup schemes. This paper presents an architecture-aware session lookup scheme for deep inspection on network processors (NPs). Test results show that the proposed session data structure and integration approach can achieve the OC-48 line rate (2.5 Gbps) with inline stateful content inspection on the Intel IXP2850 NP. This work provides an insight into application design and implementation on NPs and principles for performance tuning of NP-based programming such as data allocation, task partitioning, latency hiding, and thread synchronization. Today's firewalls and security gateways are required to not only block unauthorized accesses by authenticating packet headers, but also inspect flow payloads against malicious intrusions. Deep inspection emerges as a seamless integration of packet classification for access control and pattern matching for intrusion prevention. The two function blocks are linked together via well-designed session lookup schemes. This paper presents an architecture-aware session lookup scheme for deep inspection on network processors (NPs). Test results show that the proposed session data structure and integration approach can achieve the OC-48 line rate (2.5 Gbps) with inline stateful content inspection on the Intel IXP2850 NP. This work provides an insight into application design and implementation on NPs and principles for performance tuning of NP-based programming such as data allocation, task partitioning, latency hiding, and thread synchronization.
出处 《Tsinghua Science and Technology》 SCIE EI CAS 2009年第1期19-28,共10页 清华大学学报(自然科学版(英文版)
基金 Supported by the Basic Research Foundation of Tsinghua National Laboratory for Information Science and Technology (TNList) the National High-Tech Research and Development (863) Programof China (No. 2007AA01Z468)
关键词 session lookup deep inspection network processor performance optimization session lookup deep inspection network processor performance optimization
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  • 1范萍,李罕伟.基于ACL的网络层访问权限控制技术研究[J].华东交通大学学报,2004,21(4):89-92. 被引量:26
  • 2Intel IXP2400 Network Processor Hardware Reference Manual[M].Intel Corporation,2004.
  • 3Intel IXP2400 Network Processor Programmer Reference Manual[M].Intel Corporation,2004.
  • 4Intel Internet Exchange Architecture Portability Framework Developer's Manual[M].Intel Corporation,2004.
  • 5Intel Corp.IXP2400 Network Processor Hardware Reference Manual[Z].2003-09.
  • 6Intel Corp.IXP2400/2800 Network Processor Programmer's Refe rence Manual[Z].2003-09.
  • 7Intel Corp.Intel Internet Exchange Architecture(IXA) Portability Framework Developer's Manual[Z].2003-11.
  • 8陈红林.基于Intel IXA架构的防火墙设计[D].成都:电子科技大学,2003-04.

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