基于Verilog HDL的I^2C总线分析器

Design of I^2C Bus Analysis Based Verilog HDL

提出了采用Verilog HDL设计I2C总线分析器的方法,该I2C总线分析器支持三种不同的工作模式:被动、主机和从机模式,并提供了嵌入式系统设计接口。通过硬件总体框架分析,分模块输入,经过仿真、逻辑综合和FPGA硬件验证表明,该总线分析器与其它常用接口方式相比具有低功耗、占用资源少和功能完备等特点,并较少占用微处理器指令周期,应用在医疗检测系统中解决了增加可靠扩展平台问题。

We describe a design process of I^2C bus analysis based Verilog HDL.This bus analyzer application here provides three different operating modes：passive,active master and active slave and the interface of embedded systems components.The result of the simulations and synthesis show that the I^2C bus analyzer is steady,reliable and portable.This analysis can be used in medical multi-paprameter monitor instrument to improve the extended interface.