兼容51指令的8位MCU IPCORE设计

A design of 51 instruction compatible 8-bit mcu ip core

本文基于目前SOC系统技术的发展情况,设计一个可用于SOC系统的核,该核的指令集完全兼容于MCS-51系列的微控制器。本设计的目的在于提高MCS-51的指令执行速度的同时兼顾面积的考虑,提升其在Soc系统中的应用价值。该IPCORE采用数据总线和指令总线相分离的哈佛总线结构和全新的指令时序以及指令实现方式,并使用PLA硬布线逻辑代替微程序控制,加快了核的速度,提高了指令执行效率。所有的模块都采用vhdl硬件描述语言进行设计描述,使用EDA工具进行功能仿真、综合。

In this paper ,a MCU IPCORE used in SoC is designed. It is based on the present SoC system technology, and completely compatible with the MCS-51 series Microcontroller instruction. Our design is to speed up MCS-51 and increase its value in SoC system. The IP CORE is based on Harvard architecture, and PLA hard-wired logic instead of micro-program. All these Technologies speed up the CORE＇s speed and increase its performance. All the modules of the microcontroller are described with VHDL and synthesized with high-level synthesis EDA tools.