FPGA中嵌入式存储器模块的设计

Design of an Embedded Memory Block in FPGA

本文设计了一种基于0.13微米CMOS工艺的FPGA芯片中的嵌入式存储器模块。该容量为18Kb的同步双端口存储模块,可以配置成为只读存储器或静态随机存储器,每个端口有6种数据宽度、3种写操作模式可供选择。采用行为级与晶体管级协同仿真的方法,同时完成模块的功能验证和时序参数的提取。全定制的核心版图经过自动布局布线工具的包装,最终产生适用于特定FPGA芯片的完整版图。

An embedded memory block in FPGA is designed using 0.13-μm CMOS processing technology. The synchronous 18Kb dual-port memory supports multiple configurations. It can be configured as a ROM or SRAM and there are 6 data-widths as well as 3 write modes for each port. Mixed-level simulation integrating both behavioral and transistor levels is adopted to verify the functions and obtain timing parameters simultaneously. Custom-designed memory core is packaged by the automatic routing tool to generate the complete layouts for specific FPGA chips.