一种全数字BPSK解调器的设计与FPGA实现

Design and FPGA Implementation of All Digital BPSK Demodulator

介绍一种全数字BPSK解调器的设计及FPGA实现。该解调器采用前向开环的结构实现载波同步,与传统的闭环反馈结构相比,该解调器具有同步速度快,载波频差估计范围大等优点,尤其适合用于突发数字通信系统。测试结果表明,该解调器频差估计范围很大,可以达到符号速率的20%,抗噪声性能非常好,解调性能与理论值相比,损失小于0.5dB。

Design and FPGA Implementation of an all digital BPSK demodulator. The demodulator has a feed forward structure. Compared to the traditional feedback structure, the demodulator has the advantages of rapid carrier synchronization and large frequency offset estimation range. The demodulator could attain good performance with burst digital transmission system. The hardware test result shows that the frequency offset estimation range is large, about 20%of the symbol rate and its anti-noise performance is good, the loss is tess than 0.5 dB compared with the theoretical value.