基于FPGA的FFT处理器的设计

Design of FFT Processor Based on FPGA

本文主要研究基于FPGA的数据处理系统,内部包含一个1024点的FFT处理单元。FFT部分采用基四算法,五级级联处理,并通过CORDIC流水线结构使硬件实现较慢的复乘运算转化为移位和加减运算。双端口RAM、只读ROM全部内置在FPGA芯片内部,使整个系统的数据交换和处理速度得以很大提高,合理地协调了资源和速度之间相互制约问题。

This thesis mainly studies data acquisition, controlling and FFT based on FPGA. FFT adopts the algorithm of radix-4, 5- step cascading processing. The whole system uses pipeline pattern, practicality.. The multiplieation unit is changed to shift and addi- tion unit by CORDIC pipeline structure which is easier than multiplication for the hardware. Dual-port RAM and ROM are built in- side the system. These methods accelerate the operating and reasonably resolve the mutually restriction of resources and speed.