摘要
针对内插双正交整数小波变换(IB-IWT)的实时图像压缩特点,提出了一种FPGA设计方案.首先通过分析IB-IWT算法的特点,给出了适合硬件实现的实时图像压缩方案.然后选取高端FPGA作为硬件处理平台,对图像压缩的小波变换、小波系数编码及其小波变换的边界处理和有限字长效应等关键技术进行了研究,提出了适合于FPGA的(5,3)小波变换的快速实现方法及其小波系数的编码方法.最后,利用FPGA对图像进行了压缩.该设计方案整合标志位图思想和并行SPIHT算法结构的优势,充分利用了FPGA内部的丰富资源.实验结果表明,该方案以其低计算复杂度、低内存需求量和高实时处理速度等特点成为实时压缩算法硬件实现的优选方案.
A FPGA （field programmable gate array） design and implementation scheme is proposed according to the characteristic of IB-IWT （interpolating bi-ortbogonal integer wavelet transform） of real-time image compression. Firstly, through analysis of IB-IWT, a real-time image compression scheme for hardware implementation is put forward. Then, high performance FPGA is selected as hardware processing platform and the key technology of hardware implementation based on the algorithm is studied, such as wavelet transform, wavelet coefficients coding, boundary processing and finite word effects. Fast realization structure of （5,3） wavelet transform and wavelet coefficients coding in FPGA are proposed. Finally, the image is compressed by FPGA. By taking advantages of ideas of flag maps and parallel SPIHT （set partitioning in hierarchical trees） algorithm, the resourceful property in FPGA is greatly utilized by the scheme. The experimental results show that the scheme is greatly suitable for real-time hardware implementation due to its low computational complexity, small memory requirement and high real-time processing speed.
出处
《信息与控制》
CSCD
北大核心
2009年第1期110-114,120,共6页
Information and Control
基金
国家863计划资助项目(2003AA823050).
关键词
FPGA
IB-IWT
标志位图
并行结构
硬件实时实现
FPGA （field programmable gate array）
IB-IWT （interpolating bi-orthogonal integer wavelet transform）
flag map
parallel structure
real-time hardware implementation
