低功耗14/8bit逐次逼近式A/D转换器的设计

14/8bit SAR A/D converters with low power

设计了基于逐次逼近式架构的低功耗A/D转换器,该转换器有14/8 bit转换精度2种工作模式,其采样率分别为0～1×10^5/s和0～2×10^5/s.低功耗转换器基于0.18μm的互补金属氧化物半导体（CMOS）工艺完成版图设计,版图面积仅为0.64 mm×0.31 mm.转换器在最高性能下的积分非线性（INL）和微分非线性（DNL）最低有效位分别为0.38 LSB和0.33 LSB,电流消耗仅为2 mA.

A low-power 14/8 hit A/D converter is presented. Based on the successive approximation register （SAR） architecture, this A/D converter has two resolution modes： 14 bit and 8 bit, and its sampling rate is scalable within 0～1 × 10^5/s and 0～2× 10^5/s respectively. The low-power analog-to- digital converter （ADC） is fabricated by a 0. 18 μm complementary metal oxide semiconductor （CMOS） process. The active circuits measure 0.64 mm×0.31 mm. At the high performance point, interger nonlinear （INL） and differential nonlinear （DNL） of the ADC are 0.38 LSB （least significant bit） and 0.33 LSB respectively, and the entire ADC consumes only 2 mA current.