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片上网络虚通道分配算法 被引量：2

Virtual channel allocation algorithm for network-on-chip
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摘要 提出了一种可应用于虫孔路由片上网络(NOC)的虚通道分配算法.该算法针对传统的虚通道均匀分配方法导致的面积浪费与功耗上升的缺点,基于排队论建立了一个虫孔路由器分析模型.依据业务流量的特征,可计算路由器各输入通道的带宽利用率,仅给带宽利用率最大的输入通道分配虚通道资源.仿真结果表明,该算法使系统缓冲资源得到了更有效的利用,吞吐量得到了提高.在热点流量中,该算法在达到相同性能的前提下可节省约33.3%的缓冲资源. A virtual channel allocation algorithm for wormhole routing networks-on-chip is proposed. Traditionally, the virtual channels are allocated uniformly, which results in a waste of area and power. To remedy this situation, based on the queuing theory, we propose a router analytical model. Using this model, the proposed algorithm calculates the bandwidth usage at each router in the net- work according to the traffic characteristics of the target application, and adds virtual channels （VCs） only to the channels with the highest bandwidth usage. The simulation results show that the virtual channel （VC） allocation result is more reasonable and higher total transmission rate can be achieved compared to the uniform VC allocation. For hotspot traffic, about 33.3% savings in buffering resources can be achieved using our algorithm, in the case of achieving similar performance levels.
作者 王力纬 曹阳 李晓辉 朱小虎
机构地区 武汉大学电子信息学院 武汉大学软件工程国家重点实验室
出处 《华中科技大学学报（自然科学版）》 EI CAS CSCD 北大核心 2009年第3期54-57,共4页 Journal of Huazhong University of Science and Technology(Natural Science Edition)
基金 国家高技术研究发展计划资助项目(2002AA1Z1490)
关键词 互连网络 片上网络 虫孔路由 虚通道 虚通道分配 interconnection networks network-on-chip wormhole routing virtual channel virtual channel allocation
分类号 TP302 [自动化与计算机技术—计算机系统结构]
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参考文献10

  • 1Benini L, Micheli G D. Networks on chips: a new soc paradigm[J]. Computer, 2002, 35(2): 70-78.
  • 2Dally W J, Towles B. Route packets, not wires: onchip interconnection networks [C]//Proc of DAC. Las Vegas: IEEE Press, 2001: 684-689.
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同被引文献18

  • 1Kumar S, Jantsch A, Sonininen J P, et al. A network on chip architecture and design methodology [C] // Proceedings of the IEEE Computer Society Annual Symposium on VLSI. Pittsburgh: IEEE Press, 2002: 117-124.
  • 2Benini L, de Micheli G. Networks on chips: a new SoC paradigm[J]. Computer, 2002, 35(1): 70-78.
  • 3Henkel J, Wolf W, Chakradhar S. On-chip networks: a scalable, communication centric embedded syslem design paradigm [C] ,// Proceedings of the IEEE International Conference on VLSI Design. Mumbai: IEEE Press, 2004: 845-851.
  • 4Mullins R, West A, Moore S. Low latency virtual- channel touters for on chip networks[C]// Proceedings of the IEEE Symposium on Computer Architecture. Munich: IEEE Press, 2004: 188-200.
  • 5Nicopoulos A, Park D K, Kim J, et al. ViChaR: a dynamic virtual channel regulator for network-on-chip router[C] // Proceedings of the 39th Annual IEEE/ ACM International Symposium on Microarchitecture. Orlando: IEEE Press, 2006: 333-344.
  • 6Rahmani A M, Daneshtalab M, Safari S, et al. Forecasting-based dynamic virtual channels allocation for power optimization of network-on-chips[C]//Proc of the 22nd International Conference on VLSI Design. New Delhi: IEEE Press, 2009: 151-156.
  • 7Mirza-Aghatabar M, Koohi S, Hessabi S, et al. An adaptive approach to manage the number of virtual channels[C]// Proceedings of the 22nd IEEE Interna- tional Conference on Advanced Information Networking and Applicatlons-Workshops. Ginowan: IEEE Press, 2008: 353-358.
  • 8Huang Tingchun, Ogras U Y, Marculescu R. Virtual channels planning for networks-on-chip [C] // Proceedings of the 8th International Symposium on Quality Electronic Design. San Jose: IEEE Press, 2007: 879-884.
  • 9邢文训,谢金星.现代优化算法[M].2版.北京:清华大学出版社,2006.
  • 10洪佳杰.高性能低功耗片上网络设计中的功耗与延时模型研究[D].南京:南京航空航天大学信息科学与技术学院,2010.

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二级引证文献3

华中科技大学学报（自然科学版）
2009年 第3期

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