数字存储示波器中触发电路的FPGA设计与实现

Implementation of Trigger Circuit in Digital Storage Oscilloscope by FPGA

本文对数字存储示波器的触发电路采用全数字化设计,并用FPGA实现。所设计的触发电路主要包括触发源选择、触发比较、预触发等。先采用FPGA中RAM资源定制了一个2K字节的FIFO作为采集数据的暂存区,然后通过控制FIFO的读写,以实现触发电路的多种功能。

The trigger circuit consists of the trigger source selection circuit, trigger compare circuit, pretrigger circuit and so on. In this paper, the trigger circuit is designed by using the FPGA. The RAM in the FPGA resources customized a 2K bytes of data collection is used as a FIFO buffer. The operations of read and write to the FIFO are controlled by the trigger circuit so that the multiple functions of this trigger circuit are implemented.