Rijndael算法三级子流水线结构的FPGA实现

Three-stage sub-pipelined architecture for Rijndael based on FPGA

提出了基于FPGA的Rijndael算法三级子流水线结构的设计方案,并在CycloneII系列FPGA芯片上实现,占用逻辑单元11840余个。在三个时钟周期内完成一轮变换,与在一个时钟周期内完成一轮变换相比,提高了运算速度。该方案适用于加密、解密和密钥编排算法。该流水线结构由数据运算模块、密钥编排模块和输入输出模块组成,给出了各模块的硬件实现框图。数据运算模块完成各轮变换,密钥编排模块产生各轮变换所需要的轮密钥,输入输出模块主要完成数据输入输出格式变换。

A three-stage sub-pipelined architecture for Rijndael was proposed, which was implemented in cyclone＇s FPGA, costing 11 840 LEs. It takes three clock periods to finish a round transformation. Compared to a round transformation within a clock period, it improves the calculation speed. It can do encryption, decryption and key-expansion. The architecture includes data module, key generator module and I/O module. The key generator module generates the corresponding sub-keys concurrently for encryption or decryption.