异构多处理器体系下缓冲机制研究

Study on Buffer Mechanism for Heterogeneous Multi-Processor Architecture

嵌入式处理器不仅广泛应用于各种智能仪器中,而且作为控制接口板卡插入到PC机,形成了异构的多处理器系统。本文主要研究异构处理器间的缓冲技术,并针对PC-ARM之间的通讯问题,提出采用双端口RAM作为异构处理器间的缓冲机制。在阐述了双端口RAM的基本原理和双端口RAM的总线争用解决方案后,提出了异构处理器间双端口RAM缓冲模型,并给出了成功应用案例。在应用案例中,给出了双端口RAM缓冲区的区域划分方法——循环缓冲区法和二级缓冲——FIFO对列实现技术。

Embedded Processors are not only used in intelligent instruments, but also made into the interface card as control unit and plugged in PC slot. The later is called as heterogeneous processor architecture. In this paper, some buffer techniques are discussed for the heterogeneous multi-processor architecture, and a kind of buffer mechanism with Dual-port RAM is proposed for the communication between PC host and ARM processor. Furthermore, Dual-port RAM＇ s principle and the solution of how to share the dual-port RAM memory are also introduced.Then a new buffer model based on Dual-port SRAM is given and successfully applied to a research project as an example.In the example, a partitioning method for Dual-port RAM buffer （called loop-buffer method） and FIFO uueue are presented, and the communication is implemented between Windows PC and ARM vrocessor.