支持细粒度并行性开发的多核DSP快速核间通信机制

Exploiting Fine-Grained Parallelism with the Fast Inter-Core Communication Mechanism on Multi-Core DSPs

一些数字信号处理程序存在强数据相关性,在将这些数字信号处理程序划分到多核DSP上时,需要开发细粒度并行性,而细粒度并行性的开发需要快速的核间通信机制支持。本文提出了一种新的面向多核DSP的快速核间通信机制:标记式共享寄存器文件TSRF,TSRF由所有的DSP核共享,寄存器文件中的每个寄存器同一个有效标记位关联,该标记位提供了核间通信同步支持。本文构建了集成TSRF机制的多核DSP原型的周期精确模拟器,该多核DSP原型包含的处理器核数目为4个。通过详细模拟,我们使用数据相关性较强的数字信号处理算法:IIR滤波和ADPCM编解码,对TSRF机制的性能进行了测试,与单核DSP相比,TSDB机制性能提升分别为1.8、1.2和1.9左右。

Some digital signal processing algorithms have dependence between relatively very small amounts of computations, so partitioning these algorithms across multiple cores needs to exploit fine-grained parallelism. However, the capability of exploiting fine-grained parallelism is constrained by the fast inter-core communication mechanism. In this paper, we propose a new inter-core communication mechanism for multi-core DSP： TSRF （Tagged Share Register File）. TSRF is shared by all DSP cores, and each register in TSRF is correlated with a tag bit which provides the low cost synchronization support for inter-core communication. We construct a cycle-accurate architecture simulator for a multi-core DSP which integrates TSRF. The number of DSP cores is four. Through detailed simulation, we evaluate the efficiency of TSRF with typical digital signal processing algorithms： IIR filter and ADPCM encoder/decoder. Compared to the result on the singlecore DSP, the multi-core DSP which integrates TSRF attains the speedup of about 1.8, 1.2 and 1.9 respectively.