AVS高清视频帧间补偿结构与电路实现

Architecture and VLSI Implementation of Inter Compensator for AVS HDTV Application

设计了一种适用于AVS高清解码的高性能帧间像素补偿结构,其优点是每个时钟周期产生1个预测像素;采用双端口存储器,同时执行输入数据的接收与预测像素的计算,减少了数据延迟;像素补偿采用三级流水的插值结构提高频率,并采用三级复用的滤波单元计算1/4预测像素来节省电路开销。在VCS中对该模块进行了仿真,在0.18μm工艺下进行综合,最高频率可达到395MHz。在250MHz频率下综合面积为3.8×104等效逻辑门,具有高性能、低成本的特点,完全满足AVS高清实时解码需求。

An efficient inter predictive pixel compensator for audio video coding standard （AVS） is presented. It generates one predictive pixel result per cycle and uses dual-port memory to reduce data latency. 3-stage pipeline architecture is used to calculate compensation pixel for increasing frequency and 3-stage reusable filters are used to calculate the 1/4 predictive pixel for saving circuit cost. Simulation shows that the module implemented can achieve AVS HD real-time decoding.