高速FPGA设计中的HyperLynx仿真分析

HyperLynx Simulation Analysis of High-speed FPGA Design

随着可编程逻辑器件的发展,FPGA快速扩展着其容量和功能,其内部可编程逻辑已经达到上千万门,且内部集成了大量算法、存储器和时钟单元,功能I/O达到上千,并且支持各种端接信号和带内部终端的差分信号标准,信号速率达到千兆位每秒。高速FPGA的PCB设计逐渐成为系统设计的关键部分。重点研究了利用FPGA的IBIS模型和Mentor Graphics公司的仿真软件HyperLynx针对板级信号的实现原理进行仿真分析。

As the developement of PLD, FPGA have rapidly expanded in their capabilities and functions. Evidence of this growth is abundant whether one looks at the core programmable logic that went from tens to millions of gates with added arithmetics, memory, clocking, and processing functions or at the I/O that has gone from a few I/Os to over a thousand, supporting numerous single -ended and differential standards with on - chip terminations and data rates into the gigabit per second range. For these reasons, there is growing acceptance of FPGA as central components in system design . This paper emphasis on using the IBIS model of FPGA and Mentor Graphics＇ s hyperlynx simulaton software to simulate the signal of PCB design.