摘要
介绍了一种新的数字自动增益控制算法,在FPGA中实现了CDMA系统中大动态ADC采样结果与基站所用基带调制解调芯片CSM5000的接口,并对结果进行了仿真。相对于模拟硬件电路设计的自动增益控制(AGC)而言,采用的DAGC设计方法具有控制平坦、建立时间快、电路结构简单和成本低等特点。采用DAGC省去了模拟增益控制器件的复杂调试,提高了CDMA系统的集成度和稳定性。在最终实现的电路中,性能达到了96dB的动态范围,控制精度小于或等于0.1dB。
The paper mainly presents a new digital automatic gain control algorithm,which is applied on FPGA for the interface between data sampled from large scale ADC and CSM5000 in CDMA system, the result is simulated. The digital AGC method, which is characteristic of flat controlled response, fast speed of setup time, low cost and simple circuit architecture, is superior to the analogical AGC model. Complicated debug of analog gain control is leaved out by making use of DAGC, which also improves integration and stability of CDMA system. The implemented circuit module of digital AGC has been achieved the dynamic limits of 96dB with the flatness of 0.1dB at output signal level.
出处
《微处理机》
2009年第1期30-32,共3页
Microprocessors
关键词
基站收发信机
数字自动增益控制
现场可编程门阵列
Base transceiver system
Digital automatic gain control （DAGC）
Field programmable gate array （FPGA）
