32位RISC处理器中系统控制协处理器的设计与实现

Design of system control coprocessor in 32-bit RISC processor

介绍了基于MIPS体系结构的系统控制协处理器设计与实现,整体结构主要包括翻译后援缓冲器、协处理器控制单元、中断例外管理单元以及协处理器寄存器单元。设计使用可综合的Verilog HDL语言描述,采用Altera公司的QuartusⅡ7.2开发软件及该公司的StratixⅡFPGA器件验证实现,并主要完成了协处理器寄存器的读/写,虚拟/物理地址的转换,以及对RISC处理器的中断例外控制等功能,同时通过仿真验证其功能的正确性。

The system control coprocessor based on the structure of MIPS is described, which mainly include Translation Look-aside Buffer （TLB）, Control Unit （CPOCU）, Interrupt Exception Control（IEC）and Register. And using the Verilog HDL with the software of Quartus II 7.2 and Stratix II FPGA, it make the functions including reading/writing registers, the transition between the physical address and virtual address and the interruption or exception control. The paper also presents the simulations.