基于SYSGEN的信号滤波系统的设计与实现

Design and Implementation of signal filtering system Based on System Generator

本文提出了一种基于FPGA的FIR滤波系统设计的新方法,介绍了一种采用Xilinx公司的FPGA芯片完成FIR滤波器的设计流程,利用System Generator建模,省去了繁重的VHDL代码编写与修改过程。该方法实现简单、可靠,只需修改相应参数就可实现不同功能。仿真结果表明,选取合适的滤波参数,可以适应不同的滤波要求,提高滤波器设计和修改的速度。

This paper puts forward a new method to design FIR filter based on FPGA, which accomplishes the design flow of FIR filter on Xilinx FPGA. This method which uses System Generator to model will save you a great deal of heavy workload to program in VHDL and debug. This method is easy and reliable in implementing, it will implement deferent functions by few parameters modifyed. The simulation indicates that proper selection of filter parameters can be adapted to different demands of filter and improve efficiency of designing and modifying of filter.