CMOS分频电路的设计

The CMOS Design of Frequency Divider Based on Similar-Johnson Counter

本文讨论了用于高速串行收发系统接收端的时钟分频电路的设计。通过对扭环计数器工作原理的分析,提出了一种基于类扭环计数器的分频电路,该电路可以模式可选的实现奇数和偶数分频,并达到相应的占空比。所设计电路在SMIC 0.18um CMOS工艺下采用Cadence公司的Spectre进行了仿真,结果显示电路可对1.25GHz时钟完成相应分频。

This paper analyzes the design of frequency division circuit in the receiver of high-speed serial transceiver. Aceording to the analysis of Johnson counter, it presents a division circuit based On a counter which is similar to Johnson counter. This circuit can realize the odd and even division by mode selection, and reach the corresponding duty eycle. The CMOS realization is provided in the article, and also the simulation under SMIC 0.18um CMOS technology with Cadence Spectre. The circuit can arrive at the anticipated requirement for the 1.25GHz clock.