基于AVS标准的熵解码器硬件设计

Entropy Decoder Hardware Design Based on AVS

提出了一种基于AVS标准熵解码器的设计方案。采用桶形移位器进行移位,采用并行结构确定码长。采用算术方法对19张码表进行算术优化,从而减小了芯片面积,提高了解码速度。采用Verilog HDL语言进行源代码设计和仿真。在0.25μm CMOS工艺库下,用Design Compiler进行综合,面积为1.5万门左右,最高频率达100MHz,达到实时解码高清AVS码流要求。

An implementation of entropy decoder for AVS standard is proposed. The barrel-shifter is used for shifting the code. Parallel structure is used for determining the length of the code. Arithmetic method used for optimizing 19 code tables increases decoding speed and reduces the size of chip. The module is designed and simulated through Verilog HDL. Using Design Compiler, the design consists of 15k gates when it is synthesized based on 0.25 μm CMOS library. The highest frequency can reach 100 MHz. The realized system can achieve real-time decoding high-definition AVS code stream request.