一种基于FPGA的AES算法的低功耗实现

A low power-cost FPGA-based implementation of AES algorithm

目前网络支线上绝大部分用户面对的是千兆和百兆的以太接入网,因此设计低功耗而不影响接入网数据传输速率的AES加密芯片将具有广阔的应用前景.由此,在保证128密钥安全性的条件下,本文提出了一种将AES加密算法的128位明文分为4个32位加密单元进行处理,并通过流水线技术进一步降低功耗的AES加密芯片的实现方法.并且针对一般的FPGA结构仿真实现了上述的设计.

Present most Internet users face to Access Network with data transferring speed from 100 Mbps to 1 000 Mbps.So design a low power-cost hardware chip which implements AES algorithm with enough speed to access Internet will widely apply in future human life.With 128 bit cipher key on encryption safety,this paper presents a method for low power-cost AES algorithm implementation.128 bit plaintext is divided by four 32-bit units for AES encryption.Moreover with pipeline technology used,the power cost of FPGA decreases much.Furthermore this paper implements the above-mentioned design in simulation for common FPGA structure.