高速流水线浮点乘法器的设计研究

Research of High-Speed Pipelined Floating-Point Multipfier Design

设计了一种新颖的、支持扩展单精度43位浮点数的流水线乘法器IP芯核。该设计采用了改进的三阶Booth算法,提出了混合树形结构压缩阵列和双乘法通道6级流水线结构。经FPGA硬仿真验证表明,该乘法器运算能力达到143.6MFLO/S,比Altera公司近期提供的同类乘法器单元快47%。该设计有效地提高了乘法器的整体性能。

A novel pipelined multiplier IP chip-core which supports single extended precision 43b floating point is designed.This design takes the advantage of modified Booth3 algorithm,and proposes a hybrid tree-shaped compression array.A new architecture of double multiplication channel six-stage pipeline is also proposed in this paper.Being implemented on FPGA,the operation performance of this in multiplier achieves 143.6 MFLO/S(Million Floating Point Operations Per Second)which is 47% higher than that of the similar multiplier unit recently provided by the Altera corporation.The experimental results show that this design can efficiently enhance the overall performance of multiplier.