一种基于FPGA的硬件开环位同步电路设计与实现

FPGA Based Open Loop Hardware Bit Synchronizing Cuit

针对短时突发数据接收对位同步电路的要求,设计一种基于FPGA的硬件开环位同步电路。从时序关系,状态转化等方面分析其同步过程和原理,推导其相位误差、同步建立时间、同步保持时间等主要性能参数,并在现有通用FPGA芯片上实现完成设计方案。该同步电路完成无线数据接收中位同步从软件模块向硬件模块的转化,提高了位同步对高速数据及短时突发数据接收的适应能力,硬件测试结果验证了其正确性和有效性。

A hardware electrocircuit scheme for bit synchronization are designed to met the demands of bit synchronization little paroxysmal data receiving in wireless digital system.The principle and process of synchronization are analyzed from time sequence and state convertsion,and the main property parameter,such as Phase Error,Setup Time and Hold Time of synchronization are derived.And the plan is achieved in current FPGA Chip.The application of the scheme converts software module into hardware modules so that high-speed data or little paroxysmal data transmission can be achieved,the correctness and the validity are certified by the implementation result.