一个带有可变结构总线的常数排序处理机阵列

A CONSTANT TIME SORTING PROCESSOR ARRAY ARCHITECTURE WITH A RECONFIGURABLE BUS SYSTEM

本文提出一个具有N1+ε台处理机和带有N1+ε个1-位（二进制位）的可变结构的总线系统的SIMD阵列处理机系统．其中，ε是任意小的正常数．它具有常数步排序能力．先前具有常数步排序能力的系统[7]其处理机台数为N3，所带可变结构总线为N2个S-二进制位的可变结构总线，其中，S＝log2N．

A sorting processor array architecture with N1+ processors and a reconfigurable bussystem with N1+ 1-bit reconfigurable buses, which sorts N s-bit numbers in a constant time, isproposed in this paper, where e is an arbitrary small positive constant. Previous sorting work archivedthe constant time is on the same kind of processor array with N3 processors and N2 s -bitsreconfigurable buses, where s=log2N.