The Key Techniques of VHDL Parser's Automatic Generation

VHDL语言分析器自动生成中的关键技术

VHDL and its supporting environment are active domain in the field of logic design.In the paper the design principle and some key techniques to solve the problems on the implementation of the VHDL parser are introduced. According to the methods discussed in the paper, the VHDL parser based on VHDL IEEE 1076 standard version is implemented and a series of strict tests are done. This VHDL parser is front-end tool of the VHDL high level synthesis and mixed level simulation system developed by the Research Center of ASIC of BIT.

ＶＨＤＬ语言及其支撑环境是逻辑设计自动化中的活跃领域，本文论述了ＶＨＤＬ语言分析器的设计原理及实现中的关键技术．按照文中的方法，已实现了基于ＶＨＤＬＩＥＥＥ１０７６标准版本的ＶＨＤＬ语言分析器并对其进行了一系列严格的测试，该ＶＨＤＬ语言分析器是北京理工大学计算机科学与工程系开发的ＶＨＤＬ高级综合及混合模拟系统的重要组成部分．