应用于SoC功能验证的快速处理器仿真模型

Fast processor simulation model for SoC function verification

针对处理器仿真模型在SoC功能验证中效率低下的问题,提出了一种基于时间域和空间域仿真冗余压缩的处理器快速仿真模型.基于时间域的仿真冗余压缩方法通过监测总线工作状态,消除总线空闲下的系统冗余仿真.基于空间域的仿真冗余压缩方法通过监测程序访问存储器的地址空间,缩减访问本地存储空间时的冗余系统仿真.实验结果表明,该模型在保证仿真精度高于80%的基础上,可有效减少系统冗余的仿真事务;当2种方法联合应用时平均提高仿真速度60.27倍左右,从而提高软硬件协同设计的效率.

In order to improve the efficiency of the processor model in SoC simulation, a fast processor simulation model with two novel methods which were named as temporal redundant compression （TRC） and spatial redundant compression （SRC） was proposed. In the mechanism of TRC, idle states of the system bus were detected and all the redundant simulations in these periods were skipped. SRC monitored the address of data operation dynamically, and made processor model access internal memory when the targetaddress fell into the region of local memory. Instruction fetching and local memory accessing were both removed in system simulation. Experiments showed that these two methods can efficiently reduce redundant simulation transactions and speed up the simulation by about 60. 27 times averagely while keeping the accuracy being over 80%.