一种基于SystemC属性检查的验证方法

Verification Method Based on Property Checking of SystemC Design

当今复杂电子系统倾向于在更高抽象级进行建模,一种基于C/C++的硬件描述语言,SystemC语言变得非常重要。在此探讨了一种基于SystemC属性检查的仿真验证方法。针对电路系统的线性时态逻辑属性,定义了属性表达的基本形式,并用SystemC代码描述系统属性,在仿真中检查系统属性从而达到验证目的。首先介绍SystemC语言及一种基于SystemC的属性检查方法,讨论了现有方法的不足之处,并给出了两种改进方案,最后通过实验证实该方案的有效性,同时实验表明该改进方案在仿真性能上有很大的提高。

Today, complex systems are modeled on a high level of abstraction. In this context, C/C＋＋ based description languages,such as SystemC,become very important. A method according to property checking of SystemC design is introduced, and how to describe linear temporal logic property of circuit system is discussed. The basic form of property description is defined and the method of how to use SystemC to describe the property is elaborated. In addition,SystemC language is introduced,and the approaches of property description and property checking during simulation are discussed. The deficiencies of the current property checking are also analyzed. As a result, two improvements for property checking, and the experiment results demonstrate the effectiveness of our methods are proposed.