多层次AHB总线架构中Bus Matrix的设计和实现

Design and Implementation of BusMatrix in Multi-layer AHB

多层次AHB BusMatrix是ARM公司提出的一种高效的片上总线架构,允许多个主设备并行访问多个从设备,它能有效提高总线带宽,并增加系统的灵活性。这里使用Verilog HDL给出BusMatrix的RTL级的实现。这一实现具有很强的可配置性,支持多达16个的主设备和从设备,具有三种仲裁方式,有不少于1 440种可能的配置。详细描述BusMatrix的输入模块、译码器和输出模块的设计思想。最后用综合工具BusMatrix进行了功耗和面积的评估,可以看到其输入模块的功耗占整个设计的50%,因此将输入模块的低功耗设计作为下一阶段的工作重点。

The multi- layer AHB BusMatrix （ML- AHB BusMatrix） proposed by ARM is a highly efficient on chip bus architecture which allows parallel access paths between multiple masters and slaves in a system. The benefit of increased overall bus bandwidth,and more flexible system structure are given. The BusMartrix in register transfer level with Verilog HDL is implemented. This implementation is highly configurable, which supports up to sixteen masters and slaves and three arbitration schemes,gives at least 1440 possible configurations. How to design three main components of BusMatrix are described in details. The performance and area of the circuit with EDA tools are analysed. According to the result, the idea of enhanced design of BusMatrix is proposed.