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高速网络安全协处理器中PCI-X接口设计 被引量:1

Design of PCI-X Interface for High Speed Network Security Co-processor
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摘要 介绍高速网络安全协处理器中PCI-X接口模块的设计方法,利用IPSec和SSL/TLS2种协议优化系统,并配置各种算法引擎。协处理器采用具有更高性能的PCI-X总线接口及SoC芯片,能够同时满足PCI-X总线协议和协处理器内部的特殊传输要求。实验结果表明,该设计方法是可行的。 The method to design PCI-X interface for high speed network security co-processor is introduced, which uses two protocols such as IPSec and SSL/TLS protocols to optimize the system, and deploys different kinds of algorithm engines. The co-processor uses PCI-X bus interface and SoC chip with higher performance, which meets the requirement of both PCI-X bus protocol and the internal data transfers of co-processor. Experimental results show this method is feasible.
出处 《计算机工程》 CAS CSCD 北大核心 2009年第7期212-214,共3页 Computer Engineering
基金 国家自然科学基金资助项目(60576027 60544008) 国家"863"计划基金资助项目(2006AA01Z415)
关键词 PCI-X总线接口 密码安全 协处理器 PCI-X bus interface cipher security co-processor
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参考文献3

  • 1Wang Haixin, Yao Yue, Zhang Chunming, et al. A Novel Unified Control Architecture for a High-performance Network Security Accelerator[C]//Proc. of the Int'l Conf. on Security and Management. Las Vegas, USA: [s. n.], 2007.
  • 2Edward S, George W. PCI-X Addendum to the PCI Local Bus Specification[Z]. (1999-09-22). http://www.pressreleasepoint.com/ pcix-addendum-released-member-review.
  • 3Ravi B,Anderson D,Shanley T.PCI Express系统体系结构标准教材[M].北京:电子工业出版社,2005.

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