PCI总线高速连续采集控制逻辑研究

Research on the control logic of continuous high speed acquisition based on PCI bus

针对数据采集系统中大容量数据的高速连续传输问题,结合PCI接口芯片PCI9054与高速异步FIFO,提出了一种以FPGA器件为本地控制器的PCI总线高速连续数据采集系统的实现方法,详细分析了高速连续采集的硬件系统结构,重点对PCI本地总线接口时序做了深入研究,采用Verilog HDL硬件描述语言,引入有限状态机技术,设计实现了PCI从模式单周期与突发周期访问相兼容的逻辑控制程序。最后通过实验验证该方法的有效性。

A implementation method of continuous high speed data acquisition based on PCI Bus is proposed in this paper to deal with the problem of continuous high speed data transmission in the system of data acquisition through the FPGA as the local controller on the basis of the PCI interface chip PCI9054 and high speed asynchronous data buffer FIFO （first in first out）. With detailed analysis on the structure of hardware system, further research on the timing schedule of PCI local Bus is particularly made in the paper, by introducing the technology of finite state machine（FSM）in Verilog Hard Description Language （HDL） to realize the control logic of compatible PCI Target Single-Cycle Write and PCI Target Burst Read. Finally, the experiment and debugging are given to verify the effectiveness of the proposed solution.