考虑制程变异的全芯片漏电流统计分析

Statistical full-chip leakage analysis for manufacturing systems with process variations

为了解决在制程变异的影响下,全芯片漏电流很难被验证的难题,提出了基于新的漏电流模型的统计分析算法。建立了一个亚阈值漏电流模型以及它的参数提取方法。该模型不仅包含了小尺寸器件的量子效应和应力效应,而且能够很好地与实验数据拟合。65 nm工艺节点下由于制程变异而引起的亚阈值漏电流波动表明,主要的变异源为有效沟道长度和阈值电压的变化。模型和对变异源的研究,验证了全芯片漏电流。模拟结果和实际电路测试结果的比较,证明了该算法的正确性和有效性。

A statistical leakage methodology was developed to address the growing issue of full-chip leakage verification for actual-fabrication circuits. Both quantum and stress effects are included in the model and it accurately fits experiment data for both nMOSFETs and pMOSFETs. The model is used to study the leakage variations for the 65 nm technology. The gate length （L） roughness and variations in Vth are found to he the most important sources. An algorithm is then presented for a full-chip leakage analysis. Simulations with measured data demonstrate the effectucness of this methodology.