基于虚拟JTAG测试方法的研究

Research on Testing Method Based on Virtual JTAG

随着FPGA复杂度的提高,验证过程成为FPGA设计周期中的关键部分。文章先简介了最新的虚拟JTAG测试方法,然后对用户控制逻辑和Tcl的应用等方面进行了分析,并结合具体实例详细说明了虚拟JTAG的使用方式。实验结果表明运用此种测试方法,可以灵活进行系统级片内调试,节约测试成本,加快设计验证进程。

With the increase of FPGA＇s complexity, the certification process has become a key part of FPGA design cycle. The newest virtual JTAG test method is introduced. And then, the user control logic and the application of Tel are analyzed. In conjunction with detailed description of the specific example, it shows how to use the virtual JTAG. The experimental results show that the debug on-chip in system-level can be realized flexibly. It can save the cost and accelerate design verification process by using such testing method.