期刊文献+

SoC测试调度的进程代数模型

SoC Test Scheduling Model Based on ACSR
下载PDF
导出
摘要 功耗约束下的SoC核流水测试可避免过高功耗毁坏待测芯片,对SoC核的流水测试进行调度可合理地分配测试资源、减少测试时间.以进程代数为理论基础,提出了一种SoC核流水测试的测试调度方法.通过建立并发测试进程的时间标记变迁系统模型,形成了将前者转化为共享资源的通信代数(ACSR)描述的几个定理;建立了SoC测试调度模型;将核的流水测试映射为并发执行的进程、把测试资源建模为ACSR资源,用优先级解决测试冲突,使得功耗约束下的测试获得最大并行性,同时使测试应用时间最小.实验结果证明进程代数ACSR在处理SoC测试调度问题方面优于已有的经典算法. Pi system test app imperative for pelined test under constraint of power dissipation is preferable for minimal overall lication time to keep the chip under test from being destroyed. Reasonable scheduling is optimal SoC test automation for optimal test resources allocation and test time minimization. A SoC test scheduling model based on algebra of communicating shared resources is proposed, and related theorems for transforming timed label transition system model of concurrent core testing into ACSR descriptions are given. The pipelined tests are mapped into concurrent processes. Test resources are modeled as ACSR resources, and priorities are used to avoid test conflicts to achieve maximum test parallelism under power dissipation. Experimental results indicate the advantage of our approach to SoC test scheduling for minimal test application time over the classical solutions.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2009年第4期493-499,共7页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金(60273081)
关键词 SoC测试调度 共享资源的通信代数 流水测试 SoC test scheduling algebra of communicating shared resources pipelined test
  • 相关文献

参考文献10

  • 1Chakrabarty K. Test scheduling for core based systems using mixed-integer linear programming [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000, 19(10): 1163-1174
  • 2Iyengar V, Chakrabarty K. System on-a-chip test scheduling with precedence relationships, preemption, and power constraints [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (9) 1088-1094
  • 3Chattopadhyay S, Reddy K S. Genetic algorithm based test scheduling and test access mechanism design for system- on- chips [C] //Proceedings of the 16th International Conference on VLSI Design, New Delhi, 2003:341-346
  • 4Huang Y, Cheng W T, Tsai C C, etal. On concurrent test of core based SOC design [J]. Journal of Electronic Testing: Theory and Applications, 2002, 18(4/5): 401-414
  • 5胡瑜,韩银和,李华伟,吕涛,李晓维.基于双核扫描链平衡的SoC测试调度[J].计算机辅助设计与图形学学报,2005,17(10):2203-2208. 被引量:4
  • 6Baeten J C M. A brief history of process algebra [J]. Theoretical Computer Science, 2005, 335(2/3): 131-146
  • 7Lee I, Philippou A, Sokolsky O. A family of resource bound real-time process algebras [J]. Electronic Notes in Theoretical Computer Science, 2006, 162(1): 221-226
  • 8Koranne S. A novel reconfigurable wrapper for testing of embedded core-based SOCs and its associated scheduling algorithm [J]. Journal of Electronic Testing: Theory and Applications, 2002, 18(4/5): 415-434
  • 9Aydin H, Melhem R, Mosse D et al. Power-aware scheduling for periodic real-time tasks [J]. IEEE Transactions on Computers, 2004, 53(5): 584-600
  • 10Clarke D, Lee I, Xie H L. VERSA: a tool for the specification and analysis of resource-bound real-time systems [R]. Philadelphia: University of Pennsylvania, 1993, 1-31

二级参考文献14

  • 1Zorian Y. Test requirement for embedded core-based systems and IEEE P1500 [A]. In: Proceedings of the International Test Conference, Washington D C, 1997. 191~199.
  • 2Benabdenebi M, Maroufi W, Marzouki M. CAS-BUS: A scalable and reconfigurable test access mechanism for systems on a chip [A]. In: Proceedings of the Design, Automation and Test in Europe, Paris, 2000. 141~145.
  • 3Varma P, Bhatia B. A structured test re-use methodology for core-based system chips [A]. In: Proceedings of the International Test Conference, Washington D C, 1998. 294~302.
  • 4Marinissen E J, Arendsen R, Bos G. A structured and scalable mechanisrm for test access to embedded reusable cores [A]. In:Proceedings of the International Test Conference, Washington D C, 1998. 284~293.
  • 5Benini L, Micheli G D. Networks on chips: A new SoC paradigm [J]. Computer, 2002, 35(1): 70~78.
  • 6Chakrabarty K. Optimal test access architectures for system-ona-chip [J]. ACM Transactions on Design Automation of Electronic Systems, 2001, 6(1): 26~49.
  • 7Huang Y, Cheng W T, Tsai C C. Resource allocation and test scheduling for concurrent test of core-based SOC design [A].In: Proceedings of the IEEE Asian Test Symposium, Kyoto,2001. 265~270.
  • 8Chattopadhyay S, Reddy K S. Genetic algorithm based test scheduling and test access mechanism design for system-on-chips[A]. In: Proceedings of the International Conference on VLSI Design, New Delhi, 2003. 341~346.
  • 9Larsson E, Peng Z, Carlsson G. The design and optimization of SOC test solutions [A]. In: Proceedings of the International Conference on Computer Aided Design, San Jose, 2001. 523~530.
  • 10Zou W, Reddy S M, Pomeranz I. SOC test scheduling using simulated annealing [A]. In: Proceedings of the 21st IEEE VLSI Test Symposium, Napa Valley, 2003. 325~330.

共引文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部