扩展相容性扫描树中的测试响应压缩器设计

An Efficient Response Compactor for Extended Compatibilities Scan Tree Construction

在扫描树测试技术中,对相容单元扫描移入相同的测试向量值可以显著地减少测试应用时间,但会使测试需要的引脚数和测试响应数据量增大.为了减少扫描树测试结构需要的引脚数以及测试响应数据量,同时克服错误位扩散带来的困难,在异或网络的基础上,提出一种适用于扫描树结构的测试响应压缩器.该压缩器由扩散抑制电路和异或网络构成,通过抑制电路消除错误位扩散给测试响应压缩带来的困难.最后,用实验数据从性能上分析了该测试响应压缩器的适用性,对于ISCAS89标准电路,最高将输出压缩74倍,且没有混叠产生.

Scan tree techniques reduce test application time drastically by shifting the same test data into the compatible scan cells simultaneously. However, both its test pins and test response data volume increase. This paper proposes a test response compactor for extended compatibilities scan tree construction based on an XOR-network to reduce the test pins, test response data volume and to overcome the error bits diffuse problem at the same time. The proposed compactor consists of a diffusion control logic and an XOR-network. The diffusion control logic eliminates the error bits diffusion problem. Experimental results show that the proposed compactor brings 0 aliasing for ISCAS＇89 benchmark circuits while the compaction ratio is up to 74X.