一种基于FPGA的RTL级电路功耗评估方法

FPGA-Based Approach for RT Level Circuit Power Estimation

功耗是当前集成电路设计中应考虑的最重要因素之一。RTL级电路功耗评估可以在保证一定速度和精度的前提下对电路进行尽可能早的功耗评估。目前商业功耗评估工具对RTL级电路评估的方法多是基于软件的,因速度较慢其应用受到很大限制。提出了一种基于FPGA的RTL级电路功耗评估方法,与传统的基于软件的功耗评估方法相比,速度提高了10到100倍。速度上的优势也使该方法特别适合于研究不同激励对电路功耗的影响。

Power has emerged as one of the most important factors in designing integrated circuit.RT level power estimation provide as early as possible estimation while keeping sufficient accuracy and efficiency.Most state-of-the-art tools for RT level power estimation are software-based,whose low efficiency constrains their application.A FPGA-based approach for RT level circuit power estimation is proposed,which has speedup from 10x to 100x compared to state-of-the-art commercial power estimation tools.Speed advantages make this approach suit for research of different pattern power consumption.