超高速低功耗4：1复接器设计、封装及测试

Design,package and test of ultra high-speed low power 4:1 multiplexer

采用CSM0.35μm CMOS工艺,设计了低功耗2.5-3.125Gbit/s4∶1复接器.该芯片既可以应用于光纤通信系统SDH STM-16（2.5Gbit/s）速率级别的光发射机,又可以应用于万兆以太网IEEE802.3ae10GBASE-X（3.125Gbit/s）速率级别的通道接口发送器.系统采用树型结构,核心电路由锁存器、选择器、分频器组成,并采用了CMOS逻辑实现.最高工作速率可达3.5Gbit/s.芯片供电电压3.3V,核心功耗为25mW.该芯片采用SOP-16封装.芯片封装后焊接在高速PCB板上进行测试,封装后芯片最高工作速率为2.3Gbit/s.

A 2.5 to 3. 125 Gbit/s 4 ： 1 multiplexer using CSM （chartered semiconductor manufacturing） 0. 35 μm complementary metal oxide semiconductor （CMOS） process is described. This multiplexer is not only designed for the application of SDH （synchronous digital hierarchy） STM （synchronous transfer mode）-16 system but also for IEEE 802.3ae 10GBASE-X. The tree-type structure is adopted. The core circuits are composed of latches, selectors and a frequency divider. The core part is totally realized by CMOS logic for it has no static power consumption. Output data rate is up to 3.5 Gbit/s. The core power consumption of the chip is about 25 mW at a supply voltage of 3.3 V. Small out-line package （SOP） -16 is adopted. A high-speed printed circuit board （ PCB ） which is used in the packaged chip test is designed and produced. Output data rate of the packaged chip is up to 2.3 Gbit/s.