CMOS low-dropout regulator with 3.3 μA quiescent current without off-chip capacitor

3.3μA静态电流无片外电容的CMOS低压差线性稳压器(英文)

A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.

设计了一种用于片上系统的无片外电容的CMOS低压差线性稳压器(LDO),其输出电压为3.3V,最大输出电流为100mA.该设计可以有效地减少芯片引脚和电路板面积.通过在传统结构上使用动态摆率增强电路和嵌套式米勒补偿技术,LDO在线性和负载响应过程中都有很强的稳定性.当输出电流从100mA减小到1mA时,过冲电压被限制在550mV以内,稳定时间小于50μs.由于采用了30nA的电流基准,本设计的静态功耗仅为3.3μA.通过CSMC公司0.5μm CMOS工艺进行设计并流片验证,芯片测试结果与仿真结果吻合.