基于FPGA的RFID防碰撞算法的硬件实现

Hardware Implementation of RFID Anti-Collision Algorithm Based on FPGA

采用改进型二进制树搜索算法,优化了二进制树搜索路径、仲裁中断信道传输及高效随机数产生器的设计,用Verilog HDL语言在RTL级对全算法模块进行了描述,并用ModelSim软件进行功能仿真及时序验证,在Stratix EP1S10F484C5器件上进行防碰撞现场可编程门阵列(FPGA)综合,使射频识别技术(RFID)系统兼容基于位碰撞及非基于位碰撞两种识别机制的硬件设计得以实现.实验结果表明:该改进算法执行效率接近50%,比传统算法具有更高的时分多址(TDMA)信号利用率及平均识别效率,能满足多标签的快速准确识别,起到良好的防碰撞作用.

This paper adopts an improved binary tree-scanning algorithm, optimizes the binary tree search path, arbitration of the interrupt transmission channel and high efficient random number generator. The algorithm module is described with Verilog HDL in RTL, and functional simulation,timing verification is executed by ModelSim,and the algorithm is implemented on the field progammable gate array （FPGA） device EP1S10F484CS. It realizes the hardware system of radio frequency identification（RFID）, which supports bit-collision and unbit-collision. Simulation results show that the efficiency of the algorithm is about 50%, with a higher signal utilization and average identification efficiency than old algorithm. It can identify tags quickly and accurately, thus it plays a good role in anti collision.