一种低功耗动态可重构cache方案

Dynamically reconfigurable cache scheme with lower-power

嵌入式系统中,处理器功耗是十分受关注的,研究表明嵌入式系统中cache存储器的功耗占处理器总功耗的30%～60%。为此提出一种低功耗动态可重构的cache方案Tournament cache,该cache方案通过在传统cache结构的基础上增加三个计数器和一个寄存器,在程序运行的过程中,根据计数器统计的结果动态调整cache的相联度,使得相联度在1、2或4路之间变化,以适应不同程序段的需要,从而降低系统的功耗。实验结果表明,此cache方案对比传统的四路组相联的cache能耗节省超过40%,而且性能的降低几乎可以忽略。

In many embedded computing systems, energy consumption of processor is a major concern. Several studies have shown that cache memories account for about 30 to 60 percent of the total energy in modern microprocessors. A lower- power dynamically reconfigurable scheme named Tournament cache was presented. By adding three additional counters and a register on the basis of conventional cache structure, the Tournament cache could be configured to be direct-mapped, two-way or four-way set associative according to .the statistics results of the counter in the runtime of program to adapt to the needs of different phase of program, thereby resulting in the energy reduction of system. Experimental results show that the cache design can save the energy consumption of over 40 percent, and the performance decline is negligible.