有限扫描集成电路测试生成方法

A Novel Approach to Test Generation Based on Limited Scan Operation

本文针对集成电路测试应用时间长,导致测试费用高的问题,提出了用有限扫描操作代替全扫描操作的有限扫描集成电路测试生成方法。通过将扫描输入端、扫描选择端和扫描输出端视为电路通用输入输出端,消除了测试生成过程中扫描操作与测试应用向量之间的差别,同时在扫描操作周期和功能时钟周期上检测故障响应,有效降低了测试时钟需求,在相同故障覆盖率下,明显缩短了测试应用所需时间。基准电路实验结果表明,本文提出方法所需测试应用时间仅为传统方法的50%左右。

The long testing time for VLSI may cost significant increase of the testing expense, the problem is widely concerned recently. According to this problem, this paper proposes a novel approach to test generation for scan circuits that eliminates the distinction between scan operations and application of input vectors by taking the scan- in, scan-sel and scan-out as common input and output. The fault effect can be observed on the output of both scan operation cycle functional time cycle. This leads to very aggressive compaction on test application time cost under the same fault coverage. Experiment result of benchmark circuits shows that the test application time cost of the proposed method is about 50% of the conventional methods only.