一种支持预搜索的面积紧凑型BCH并行译码电路

An area-efficient parallel BCH decoder supporting foresighted error search

在支持预搜索的面积紧凑型BCH并行译码电路中,采用双路选通实现结构,在校正子运算电路的输入端完成被纠码序列与有限域常量的乘法,简化了电路结构;在实现IBM迭代算法时,为了压缩实现面积,复用一个有限域GF(2n)上的二输入乘法器,一轮迭代运行多拍运算;设计了全组合逻辑预搜索模块,加快了BCH截短码的搜索速度。同现有技术相比,该译码电路实现面积紧凑且关键路径短。综合与静态时序分析结果表明,对于512字节的信息元和8-bit的纠错能力,该译码器在80MHz工作频率下符合时序要求;在TSMC0.18μm工艺库下仅需约14800门,满足目前大容量存储设备对数据可靠性和成本控制的要求。

An area-efficient parallel BCH decoder that supports foresighted error search is presented in this paper. For simplifying syndrome operation circuit, the diplexers are used to do multiplication between receiving sequence and constants of Galois field. Within the inversionless Berlekamp-Massey architecture, a finite-field multiplier is used repeatedly to perform multi-clock-cycle operations in each round of iteration, which contributes to the area-efficient implementation. A foresighted error search module is added to Chien search circuit to improve error search speed of shortened BCH code. Compared with the existing techniques, the proposed BCH decoder bears compact area and short critical path. Based on TSMC 0.181am standard cell library, this BCH decoder for 8-bit correction per 512Bytes only costs 14800 gates under 80MHz clock, which can meet the error control requirements of current mass-storage devices.