基于最佳交换递减的芯核测试链平衡划分

Wrapper chain balance partition for cores based on best interchange decreasing

满足TAM宽度约束的芯核测试链平衡划分,可以降低SoC测试应用时间和存储开销。针对测试链平衡划分问题,建议了一种改进的求解方案。建议方案首先应用LPT算法得到初始解,然后通过迭代技术,从当前配置中选取二条测试链,应用提出的最佳交换递减算法对其内部相关的一对单元实施最佳交换,从而快速平衡测试链。将建议方案用于ITC’02基准电路芯核的测试链平衡划分。实验结果表明,与现有技术比较,建议方案可以产生更平衡的测试链划分,从而有效地降低芯核测试应用时间。

In the core-based SoC testing, wrapper chain balance partition for cores with TAM width constraint makes SoC test application time and memory overhead low. An improved scheme for designing balanced wrapper chains is proposed. Starting with a primary partition that is created by using the known LPT algorithm, the proposed scheme optimizes the current partition through the best interchange decreasing algorithm called by iterative operation in which a pair of wrapper chains with maximum difference in length is selected and the optimal two cells are inter- changed between the two chains, rapidly balancing the wrapper chains. The proposed scheme to the cores of 1TC＇02 benchmarks for wrapper chain balance partition is applied. The experimental results show that compared with the pre- viously presented techniques, the proposed scheme can create more balanced wrapper chains, therefore reduce test ap- plication time of cores effectively.