具有误差修正的神经元MOS数模转换器

A Digital-to-Analog Converter(DAC) with Error Correction Based on Neuron-MOS(νMOS)

基于神经元MOS(νMOS)加权运算的功能设计一种结构简单的新型数模转换器。该转换器通过附加电路来修正MOS管阈值电压、减小积分非线性和微分非线性以及输入栅电容精度工艺偏差等影响,使输出误差限定在0.5LSB以内。在转换时间分别为100ns、50ns两种情况下,采用Charted 0.35μm工艺、用Candence spectre工具对其动态特性进行了模拟研究,结果表明:在转换时间为100ns的输出误差均在0.5LSB以内。

A novel DAC with simple architecture is designed based on vMOS with computing the weighted computational function. Some performances such as integral nonlinearity, differential nonlinearity and deviations of process impacting on gate capacitance precision are improved by adding additional circuitry in the DAC, whereby revising the threshold value to make the error of analog result within -0.5 to 0. 5LSB. The DAC dynamic characteristics in the converting times being 50ns and lOOns, are studied separately. The Chrted 0. 35 μm technology, and Candence spectre tool are adopted to carry out the simulation research. The results indicate that the output errors are within 0. 5LSB when the converting time is 100ns.