AVS熵编码器的VLSI设计

The VLSI Design of AVS Entropy Coder

针对AVS实时高清编码器的设计要求,提出了一种高效的AVS熵编码器的VLSI设计方案.首先,基于硬件的流水线操作和计算的并行性,修改原有的针对软件设计的串行算法为具有一定并行度的并行算法;其次,考虑硬件实现的代价,简化了熵编码器在模式决策阶段预编码的VLSI设计,因为预编码只计算编码系数所用比特数,而无需知道编码码字;而且,对于简化的预编码,熵编码所涉及的查表运算都可以改为只使用逻辑判断来实现,大大节约了硬件的存储空间;同时,数据流使用8像素并行的流水线设计,每个时钟处理8个系数,更进一步提高了硬件处理速度.AVS熵编码器包括Zig-Zag扫描得到每个系数的Run和Level,查询当前码表得到每个(Run,Level)的CodeNumber和得到每个CodeNumber的比特串,此流程与其他编码器的VLC类似,所以该VLSI设计同样适用于其他编码器,如H.264/AVC和MPEG2/4.软件测试和RTL仿真的结果都符合AVS编码标准和满足硬件加速的要求.

For the hardware accelerator of AVS high definition video eneoder （AVS-HD）, an efficient VLSI design for AVS entropy coder （2D-VLC） is provided. Firstly, due to the pipeline operation and parallel processing of hardware, the corresponding parallel algorithm from the original serial algorithm based on software architecture is proposed. Secondly, the VLSI design of entropy coder for mode decision is simplified with only logical operations, which can save much hardware memory. In the stage of mode decision, the bit-width of each DCT coefficient is only needed without the knowledge of its whole symbols, so the pure logical operations instead of looking up table required by the final entropy encoder are employed. Using the proposed hardware accelerator of AVS entropy coder, the computing complexity and memory requirement of hardware are both reduced. Moreover, in the VLSI design, the processing of hardware is further accelerated by employing 8-pixel parallel pipelining design. In such pipelining design, 8 DCT coefficients after quantization are processed in one time clock. For VLC of AVS, the CodeNumber of each （run, level） which is derived from zigzag, is obtained by looking up VLC tables. And then, each CodeNumher is mapped into code word written into the final bit stream. Such processing is same as those of other VLC coders, so the VLSI design can be used in other video coding standards, such as H.264/AVC and MPEG2/4. Finally, the result of software and RTL simulation indicate that the VLSI design is absolutely consistent with the AVS standard, and satisfied with the requirement of hardware accelerator.