DSP内嵌PLL中的CMOS压控环形振荡器设计

Design of CMOS Ring VCO of PLL Embed in DSP

介绍了一种用于DSP内嵌锁相环的低功耗、高线性CMOS压控环形振荡器。电路采用四级延迟单元来获得相位相差90°的正交输出时钟,每级采用调节电流源大小,改变电容放电速度的方式。基于SMIC0.35μmCMOS工艺模型的仿真结果表明,电路可实现2MHz至90MHz的频率调节范围,在中心频率附近具有很高的调节线性度,且总功耗仅为3.5mW。

This paper presents a low power and high linearity CMOS ring VCO,which is applied in the PLL embed in the DSP. Four stage of delay elements are adopted to generate quadrature output clock by method of adjusting the current source and altering the speed of capacitor discharge. The simulation results based on SMIC 0.35μm CMOS process show that the VCO have a wide tuning range from 2MHz to 90MHz, and with high linearity near the center frequency, its total power consumption is only 3.5mW.