适用于流水线ADC的高性能采样/保持电路

High Performance Sample and Hold Circuit for Pipelined ADC

介绍了一种利用双采样技术的高性能采样/保持电路结构,电路应用于10bits50MS/s流水线ADC设计中。电路结构主要包含了增益自举运算放大电路和栅压自举开关电路。增益自举运算放大电路给采样/保持电路带来较高的增益和带宽,栅压自举开关电路克服了多种对开关不利的影响。设计还采用了双采样技术,使采样/保持速率大大提高。设计在SMIC0.18um工艺下实现,工作电压为1.8V,通过仿真验证。本文设计的采样/保持电路可以适用于高速高精度流水线ADC中。

A high performance sample-and-hold circuit with the double-sampling technology is presented in this paper, it is usually used in 10 bits 50MS/s pipelined ADC. This circuit includes gain-boosted operational amplifier and the bootstrapped switches. Using gain-boosted op amp increases the gain and bandwidth ,bootstrapped switches conquer several kinds of bad infections on switches. The sample rate increases by using sample and hold technology. And it is simulated in SMIC 0.18um CMOS process ,which operates on 1.8V power supply, .The result shows that it is suitable for the high speed and high precision pipelined ADC.